A semiconductor integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductor or insulation material layers on a silicon wafer. After each material layer is deposited, the material layer is etched to create circuitry features. As a series of material layers are sequentially deposited and etched, the outer or uppermost surface of the semiconductor integrated circuit, i.e., the exposed surface of the material layer becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the semiconductor integrated circuit fabrication process. Therefore, there is a need to periodically planarize the exposed material layers.
Chemical mechanical polishing (CMP) process is one accepted method of planarization. This planarization method typically requires polishing slurry, including at least one chemically reactive agent, and abrasive particles supplied to the exposed surface of the material layer against a rotating polishing pad. However, there are problems and drawbacks in CMP process, for example, since variations found in the initial thickness of the material layers, the slurry composition, the polishing pad condition, the relative removing speeds between the polishing pad and the different material layers, and the load on the substrate can cause variations in the material removal rate, thus it is difficult to determine whether the polishing process has reached completion, i.e., whether a material layer has been planarized to a desired flatness or thickness in order to globally planarize the semiconductor integrated circuit, whereby merely a local planarization of semiconductor integrated circuit is thereby accomplished, and step height that may adversely effect the performance of the subsequent process for fabricating the semiconductor integrated circuit occurs between the local planarization area and the peripheral area that is not equally or sufficiently planarized.
Therefore, there is a need of providing an improved method for planarizaing semiconductor devices to obviate the drawbacks encountered from the prior art.